Can I access VHDL record outputs from a Verilog module?

Question

I have a top level Verilog module that instantiates a VHDL block with a few outputs that are records.

Is there a good way to access these records from my Verilog top, or am I better off just breaking the records apart?

Answer 1

You can (with caveats). Create a "struct" of the same type as the "record". These two will map 1:1 as long as you do not reorder the connections. Caveat being if your tool actually supports it.