what does FFd1 mean in VHDL Warning FF/Latch has a constant value of 0

Question

I'm trying to implement a finite state machine identifier with xilinix 10.1 I've seen those errors in previous questions but the answers didn't include my question.. I'm not searching for an answer but rather a meaning for the FFd1 part

The following error is generated

WARNING:Xst:1293 - FF/Latch <machine1/current_state_FFd1> has a constant value of 0 in block <Main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <machine1/current_state_FFd2> has a constant value of 0 in block <Main>. This FF/Latch will be trimmed during the optimization process.

this is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity M_1 is
    Port ( x : in  STD_LOGIC;
       clk : in  STD_LOGIC;
       state : out  integer range 0 to 5 := 0;
       z : out  STD_LOGIC );
end M_1;

architecture Behavioral of M_1 is

 type state_type is (A, B, C, D);
 signal next_state, current_state: state_type := A;

begin

process(clk) is
begin
if (clk = '1' and clk'event) then
    current_state <= next_state;
end if;
end process;

process(x,current_state)
begin
case current_state is
    when A =>
        if(x='0') then
            next_state <= B;
            z <='0';
        elsif(x='1') then
            next_state <= C;
            z <='1';            
        end if;
    when B =>
        if(x='0') then
            next_state <= C;
            z <='1';
        elsif(x='1') then
            next_state <= D;
            z <='0';            
        end if;
    when C =>
        if(x='0') then
            next_state <= A;
            z <='0';
        elsif(x='1') then
            next_state <= D;
            z <='1';            
        end if;
    when D =>
        if(x='0') then
            next_state <= B;
            z <='0';
        elsif(x='1') then
            next_state <= C;
            z <='0';            
        end if;
    end case;
end process;

process (current_State) is
begin
    case current_state is
    when A =>
        state <=0;
    when B =>
        state <=1;
    when C =>
        state <=2;
    when D =>
        state <=3;
    end case;
end process;

end Behavioral;

can anyone tell me

• What does current_state_FFd1 and what's the difference between it and current_State_1 ?
• how can i solve this error ?

Thanks inadvance

Answer 1

The "current_state" signal is mapped onto a 2-bit flip-flop primitive by the CAD tools. The flip-flop will look something like the FD16CE primitive, shown here.

The flip-flop will take 2 data inputs (current_state_FFd1 and current_state_FFd2) and a clock, and produce two data outputs (current_state_FFq1 and current_state_FFq2). The inputs determine the value of the current_state signal sampled at the next clock edge, and the outputs reflect the current state.

The message you're seeing suggests that the CAD tools can prove that "current_state" never changes from the "00" encoding ("A" in your enumerated type), and so the flip-flop can be optimized away with a hard-wired output of "00".

The VHDL you posted looks reasonable -- changes on the 'x' input should cause a change in current_state. I'll bet the 'x' input is somehow hard-wired to 0 in higher-level VHDL (or in your testbench.)