Simple adding don't work, timming issue

Question

First there is this simple adder entity:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

entity adder is
    Port ( a : in  STD_LOGIC_VECTOR(31 downto 0);
           b : in  STD_LOGIC_VECTOR(31 downto 0);
           alu_out : out  STD_LOGIC_VECTOR(31 downto 0) := (others => '0')
           );
end adder;

architecture Behavioral of adder is
  signal result_ext:STD_LOGIC_VECTOR(32 downto 0) := (others => '0');
  signal result:STD_LOGIC_VECTOR(31 downto 0)     := (others => '0');
begin

  process (a,b)
  begin
    result_ext <= std_logic_vector(signed('0' & a) + signed('0' & b));
    result     <= result_ext(result'left downto 0);

    alu_out <= result;
  end process;
end Behavioral;

And test bench:

-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS         

    signal a : STD_LOGIC_VECTOR(31 downto 0);
    signal b : STD_LOGIC_VECTOR(31 downto 0);
    signal alu_out : STD_LOGIC_VECTOR(31 downto 0);
  BEGIN
    ADDER : entity work.adder port map(
      a => a,
      b => b,
      alu_out => alu_out
    );



  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        a <= B"0000_0000_0000_0000_0000_0000_0111_1010";
        b <= B"0000_0000_0000_0000_0000_0000_0000_1011";

        wait for 100 ns; -- wait until global set/reset completes

        report "alu_out = " & integer'image(to_integer(signed(alu_out)));

        wait; -- will wait forever
     END PROCESS tb;
  --  End Test Bench 

  END;

I get report output:

Finished circuit initialization process.
at 100 ns: Note: alu_out = 0 (/testbench/).

If I don't initialize result signal I get Undefined. So problem is that I don't get result in the end.

I use iSim and Xilinx.

Also if someone have some good links to some short and effective material on VHDL, feel free to post it.

Answer 1

The issue is that you are using signals for result and result_ext when you wanted their immediate value for that cycle of the process. Variables update immediately and you can access their values in the current cycle of the process.

Try this out, I think it fixes the problem you are having:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity adder is
    Port ( a : in  STD_LOGIC_VECTOR(31 downto 0);
           b : in  STD_LOGIC_VECTOR(31 downto 0);
           alu_out : out  STD_LOGIC_VECTOR(31 downto 0) := (others => '0')
           );
end adder;

architecture Behavioral of adder is


begin

  process (a,b)
    variable result_ext:STD_LOGIC_VECTOR(32 downto 0) := (others => '0');
    variable result:STD_LOGIC_VECTOR(31 downto 0);
  begin
    result_ext := std_logic_vector(signed('0' & a) + signed('0' & b));
    result     := result_ext(result'left downto 0);

    alu_out <= result;
  end process;
end Behavioral;

As for reading material, the VHDL cookbook is not bad: VHDL Cookbook