I'm using Icarus verilog to simulate a reasonably complex design. I find that in some rare cases my simulation gets "stuck", i.e., the clock doesn't tick any more and none of the signals appear to change. I suspect this is because I have a combinational logic loop somewhere in my design. The problem, of course, is that I have no idea where.
Is there a systematic method debugging this? I'm just staring really hard at the code, but I'm unable to make any progress. Any suggestions on things I could try are much appreciated.
When you run a simulation, dump a VCD file. If you have an infinite loop, you will see the VCD file size continue to grow without a new time being written to the file. Times are indicated by # at the beginning of a line. You will be able to determine which signals are changing without time advancing.