xilinx Examples and Free Source Code

"logical root block and symbol is not supported in target" error in ISE Design Suite 14.7...

fpga xilinx spartan

Simple code yielding error even though syntax seems correct (ISE VERILOG)...

verilog xilinx xilinx-ise

Is There Any Limit to How Wide 2 VHDL Numbers Can Be To Add Them In 1 Clock Cycle?...

vhdl fpga xilinx

How to find dma_request_chan() failure reason details?...

linux-kernel linux-device-driver embedded-linux xilinx zynq-ultrascale+

FPGA logic cells...

logic cell fpga xilinx zynq

Efficient implementation of matrix multiplication ARM cortex A9 - Xilinx SDK...

c arm linear-algebra xilinx zynq

Vitis: Store 16 byte variable into 4 32-bit registers...

fpga xilinx vivado zynq

32-bit adder subtractor model compile error: Illegal Lvalue...

verilog fpga xilinx

Typecasting uint8_t vector to ap_uint<128> openCL...

c++pointers fpga xilinx

What could cause an extra bit to be added to a result in a non-blocking assignment?...

verilog cpu-architecture xilinx

16bit multiplier vhdl code synthesize error...

vhdl xilinx modelsim xilinx-ise synthesize

Integer output turns to binary in synthesize ISE...

vhdl xilinx modelsim xilinx-ise

Multiplexer is not simulating changes...

embedded vhdl fpga xilinx vivado

What to do when a latch cannot be avoided?...

hardware verilog fpga xilinx

DMA writing to allocated memory misses the first two adresses on the first write...

c arm fpga xilinx

How to return record with unconstrained 2d array from a function...

vhdl xilinx vivado

How to implement HDMI pass-through on XILINX FPGA (Artix-7)...

verilog xilinx hdmi pass-through

Xilinx FFT v8.0 core example testbench...

fft xilinx

Applying simple inversion (NOT function) to OBUFDS...

fpga xilinx vivado

How to find dot product of two vectors in vhdl?...

vhdl product xilinx

Programming multiple devices parallelly using Vivado...

tcl xilinx vivado xilinx-ise

How can I make each module instance read from a unique file?...

verilog system-verilog xilinx iverilog

Artix-7 LUT usage too high for 6-input 1-output logic...

vhdl fpga xilinx

SystemVerilog Initialize multi dimensional parameterized array in...

verilog system-verilog xilinx

Linux CONFIG_PREEMPT_RT for a quad core ARM A53 (newbie doubts)...

linux linux-kernel real-time xilinx preemption

Sine of the signal in Xilinx Simulink...

matlab verilog fpga simulink xilinx

VHDL: Button debouncing (or not, as the case may be)...

vhdl fpga xilinx vivado debouncing

Unexpected waveform is coming out, designing CPU...

verilog xilinx

Why result Q is X?...

verilog simulation system-verilog xilinx hdl

Xilinx Zynq peripheral drivers...

driver xilinx zynq