vhdl Examples and Free Source Code

How to switch between datasamples in VHDL?...

vhdl fpga

In VHDL, Can I use signal'event if signal is not a clock?...

vhdl

Random number generator in VHDL...

random vhdl

How to compare two circuits based on their utilization...

vhdl fpga xilinx vivado

VHDL equivalent to Verilog "10'h234"...

vhdl verilog

What's the VHDL equivalent of __FILE__?...

vhdl

Generate clocks with ratio for testbench...

vhdl clock

I'd like to display the segment according to differnet clocks, but I can't...

vhdl

How to remove VHDL type mismatch error due to std_ulogic type does not match integer literal?...

vhdl

VHDL - GHDL Initialise std_logic_vector with smaller bit length...

vhdl ghdl

I need to select certain digits from a floating number. Is it possible? if yes, how?...

floating-point vhdl

VHDL Pre-loading RAM Memory with MIF File...

vhdl ram modelsim quartus

How to split the 8 bit input into two 4 bit data...

vhdl

I put scrambler and descrambler module in vhdl respectively but the result of descrambler is not as ...

vhdl ethernet scramble raw-ethernet

sintaxis error that i can t understand with port map...

vhdl vivado

The components of a 1-bit ALU diagram...

vhdl alu

Why does Quartus throw an error at my if-statement?...

vhdl

assign data(i) into std_logic_vector(0 downto 0) in vhdl...

vector vhdl type-conversion

How to send only one "1" in output even when the entry stays on "1"...

vhdl

How to fix "Indexed name is not a std_logic_vector" error in my code...

vhdl xilinx

Is there a way to print an assert only once at the beggining of a simulation in vhdl?...

report vhdl

How to set branch in case statement from a constant? ERROR: choice must be locally static expression...

vhdl ghdl

How can I use the operation "+" in vhdl?...

compiler-errors vhdl quartus

Assigning values to signals within for-generate statements...

vhdl variable-assignment generate

VHDL What does this error mean, Net, "Name", which fans out to "*name*", cannot ...

vhdl quartus

Loop for lines and for position of lines...

vhdl

Bidirectional databus design...

vhdl

Putting a 5-bit value to a byte in VHDL - Will this generate a latch?...

byte vhdl bit

How can I solve the errors of my code in VHDL?...

syntax-error vhdl quartus

How to attach a parity bit to a given 4 bit std_logic_vector?...

vhdl