vhdl Examples and Free Source Code

Error with VHDL integer signal connecting Verilog integer input...

vhdl fpga xilinx

VHDL code for turning 50MHz into 38KHz doesn't work...

vhdl

How can you get a binary number with n number of '1's in VHDL?...

vhdl

How do I add the bits of a vector and at the same time save the value in a vector signal? I use goog...

vhdl

Driving record elements through procedures from different processes in VHDL...

vhdl

Breaking out of a procedure in VHDL...

vhdl fpga

Does VHDL have a ternary operator?...

vhdl ternary-operator

Multidimensional array partial assignment in VHDL...

arrays multidimensional-array vhdl variable-assignment

Incrementing Seven Segment by Using Push Buttons...

button push vhdl synclock debouncing

Can't add std_logic to unsigned...

vhdl

VHDL Configuration Across Block Statements...

vhdl

Writing a code for a CRC using D-FlipFlop in VHDL...

vhdl

Wait for input state change to start process...

vhdl xilinx-ise

No function declarations for operator + error in VHDL...

vhdl

Clock based 8 bit prime number detector...

vhdl primes clock division

VHDL: formal port 'portName' has no actual or default value...

vhdl vivado

How to add '0' to between every 2 bits of a logic vector...

vhdl fpga

Simulate Xilinx FIR compiler with a COE file using GHDL...

vhdl ghdl

"Readline called past the end of file" error VHDL...

vhdl fpga

If sensitivity list in VHDL is not synthesizable, why does it gives an error due the Analysis and Sy...

vhdl intel fpga intel-fpga quartus

How do I reduce redundancy in state logic for repeated processes (handshakes)?...

vhdl

How FPGA inferrs the VHDL constatns in the Design after synthesis...

vhdl fpga

How does this SIPO Works?...

vhdl modelsim

VHDL: Correctly way to infer a single port ram with synchronous read...

vhdl fpga vivado

How can I get the index of a one-hot encoded vector without using a for-loop?...

vhdl hdl

What is the best way to reset an array of integers in vhdl?...

arrays vhdl reset

Slice from a matrix to a vector in VHDL2008...

matrix multidimensional-array vhdl slice

'Opt_Design Error' in Vivado when trying Run Implementation...

vhdl uart xilinx vivado

Delay in Simulation of Output with regard to Input...

vhdl modelsim

VHDL way to group constants together...

vhdl constants