vhdl Examples and Free Source Code

I have the following errors appearing on my code, I don't know what they mean neither know how t...

vhdl active-hdl

Structural 4 bit ring counter with D flip flop. VHDL / GHDL...

vhdl counter ghdl

Cannot Synthesize Signal...

vhdl fpga digital

In VHDL, how do I detect if a binary input is divisible by 3 or 4?...

vhdl fpga

Programming an FPGA?...

vhdl fpga

Delaying the clock by a fraction of the period...

vhdl digital-logic

IS_X function synthesis...

vhdl

Structural Ring Oscillator VHDL...

vhdl

[VHDL]Using signal to drive output ports,why are the output ports not visible?...

vhdl

VDHL error: converted type of object near text or symbol "UNSIGNED" must match std_logic_v...

compiler-errors vhdl

Too many bonded comps of type "IOB" found to fit this device when I design a cpu use fpga...

vhdl fpga

VHDL: Combining multiplication and slicing into one line...

vhdl

Rectangle/Box Collision in VHDL...

collision-detection vhdl collision bounding-box

When should I use std_logic_vector and when should I use other data types?...

integer port vhdl unsigned signed

Translating a VHDL code to Verilog compilation error...

vector concatenation vhdl verilog

corresponding expression between Verilog and VHDL...

vhdl verilog fpga

How combine multiple VHDL codes to make one system...

vhdl

Width mismatch in assignment: VHDL...

vhdl

waveform does not work properly for some operations...

vhdl modelsim waveform

VHDL counter simulated using a test bench giving 'Uninitialized' for the output, how is this...

vhdl counter simulation vivado test-bench

An issue regarding multiple drivers on a wire, error: [DRC MDRV-1] Multiple Driver Nets: Net led_OBU...

vhdl fpga vivado

16bit multiplier vhdl code synthesize error...

vhdl xilinx modelsim xilinx-ise synthesize

vhdl signed and unsigned type endianess...

vhdl endianness signed

Clock divider in vhdl from 100MHz to 1Hz code...

vhdl fpga clock

Generating second counter in VHDL...

timer vhdl counter

Integer output turns to binary in synthesize ISE...

vhdl xilinx modelsim xilinx-ise

Multiplexer is not simulating changes...

embedded vhdl fpga xilinx vivado

Problem in VHDL: led tratrix displayed even button wasn't pressed...

button vhdl intel-fpga

How to convert a VHDL code in Verilog using Icarus Verilog?...

vhdl verilog icarus

VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?...

integer logic width vhdl synthesis