Compile thumb1 only...

Mysterious ARM Opcode...

How is this ARM (Thumb) LDR Instruction being calculated?...

Is it redundant to check if a modulo operation is needed, then performing it?...

Why the Link register in FIQ mode will be instruction address plus 4 in thumb mode instead of instru...

Is CMPS a valid ARM/THUMB instruction?...

Ordering of registers in PUSH and POP brackets...

Loading a the address of a pointer into a register inline thumb assembly...

Why do forward reference ADR instructions assemble with even offsets in Thumb code?...

What is the difference between the ARM, Thumb and Thumb 2 instruction encodings?...

ARM-C Inter-working...

Using B instructions in Cortex-M3 (thumb)...

Writing data to absolute address...

Simple example of Table Branch Byte (TBB) in arm thumb...

Can an x86_64 and/or armv7-m mov instruction be interrupted mid-operation?...

How to interpret the assembly boot code with ".word"...

How do I optimize a block copy and right shift + saturate to max=5, for Cortex-M3...

How do I reduce execution time and number of cycles for a factorial loop? And/or code-size?...

Why there is a dead loop in the generated assembly for a Cortex-M interrupt handler?...

ARM GCC + Cortex M4: Calling address as function generates BLX instead of BL...

Why MOV instruction is replaced by ADD instruction...

How does the arm-none-eabi-as choose section alignment?...

STM32 sometimes hardfault on reboot (thumb instruction issue?)...

How much exception vectors should I fill in the firmware?...

How to know if ARM or Thumb mode at entry point of program...

ARM Thumb GCC Disassembled C. Caller-saved registers not saved and loading and storing same register...

Why does a Cortex-M4 include ARM to Thumb glue in the linker script...

Detecting Thumb-2 instruction and location of PC offset...

When are GAS ELF the directives .type, .thumb, .size and .section needed?...

ARM PC value after Reset...