What is the maximum possible IPC can be achieved by Intel Nehalem Microarchitecture?...

Number of banks in Nehalem l2 cache...

floating point operations per cycle - intel...

Unexpectedly large number of TLB misses in simple PAPI profiling on x86...

Minimizing inter-core Communication in a NUMA architecture...

Mapping of memory addresses to physical modules in Windows XP...

Memory access by multiple threads...