iverilog Examples and Free Source Code

Sync RAM related...

verilog iverilog

Assign value to only one bit in a vector module output...

verilog iverilog

How to know what control signals a MIPS instruction generates?...

assembly verilog mips cpu-architecture iverilog

Verilog Error: "Syntax in assignment statement l-value." when writing a simple alu...

syntax-error verilog iverilog

How does verilog treat input values to if statements in always_ff blocks...

verilog system-verilog iverilog

I am trying use the output of a 16-bit encoder as to give input to the register (PIPO)...

verilog test-bench iverilog

Error: Unable to assign to unresolved wires...

verilog system-verilog iverilog

Error launching EPWave: [Could not parse file: $timescale not found in the header.]...

verilog system-verilog iverilog

Why are the bits in this Verilog wire assigned as 'z'?...

binary verilog iverilog

Error compiling code due to direction declaration...

verilog iverilog

Implement a state machine in Verilog using a 2D array as transition table...

arrays verilog system-verilog state-machine iverilog

What is ''_'' in Verilog?...

verilog system-verilog iverilog

Trying to simulate JK-FF with gate level code...

verilog iverilog

verilog alu design why all my output result is always 00000000...

verilog iverilog

alu.v:55: syntax: error: Invalid module instantiation and it say "I give up."...

verilog iverilog

Icarus Verilog warning $readmemh: Standard inconsistency, following 1364-2005...

verilog iverilog

Test for a 8-bit full adder giving x instead of numbers...

verilog iverilog

Why does iverilog generate a syntax error for always_ff?...

verilog system-verilog iverilog

Problems running a test in Verilog...

testing verilog system-verilog test-bench iverilog

I can't compile a .sv file (SystemVerilog)...

system-verilog iverilog

Arbitrary Counter only displaying zeros...

verilog counter iverilog

iverilog testbench module with outputs...

verilog fpga iverilog

Verilog code compiles without error but no output...

verilog iverilog

Rotations Operations for 16bit ALU using multiplexers (updated question)...

verilog alu iverilog

Icarus verilog: reg show; cannot be driven by primitives or continuous assignment...

system-verilog iverilog

How can I make each module instance read from a unique file?...

verilog system-verilog xilinx iverilog

8 bit sequential multiplier using add and shift...

verilog sequential test-bench iverilog

Why I can not copy a content of register to another one in "always" block in Verilog?...

verilog fpga yosys iverilog

Verilog error handling two posedge signals in "always" block...

verilog fpga iverilog

How can i list all hierarcheis of modules/submodules in verilog/system verilog?...

verilog system-verilog iverilog