intel-fpga Examples and Free Source Code

Trying to implement an Alarm Clock in Verilog, my clock works but my alarm doesn't...

verilog clock alarm intel-fpga

Quartus does not allow using a Generate block in Verilog...

verilog fpga hdl quartus intel-fpga

VHDL with-select error expecting "(", or an identifier or unary operator...

vhdl fpga quartus intel-fpga

Full Adder Sum Off by One Clock Cycle...

verilog modelsim intel-fpga quartus

Quartus Prime throwing an error at a $error command...

verilog fpga system-verilog quartus intel-fpga

ModelSim simulation works but FPGA fails. What am I missing?...

verilog fpga modelsim quartus intel-fpga

Driving an LED from a switch...

verilog intel-fpga

What kind of file for passive parallel loading of Cyclone 10 FPGA?...

fpga intel-fpga

How do I format an SD Card for use with the Altera DE2-115 demonstration music player project?...

system-verilog quartus intel-fpga

How to write Thread application in DO file of Model-sim 10.5c using TCL?...

tcl fpga modelsim intel-fpga

How to fix Error (10170): Verilog HDL syntax error at <filename> near text "("; expe...

verilog system-verilog intel-fpga quartus nios

Low Pass Filters in FPGA's...

vhdl intel-fpga

Flash / Run Altera Cyclone IV with OpenOCD...

fpga intel-fpga openocd flashing

How to display decimal equivalent (0-63) on two 7-segment displays using 6 switches as bits?...

verilog intel-fpga quartus

If sensitivity list in VHDL is not synthesizable, why does it gives an error due the Analysis and Sy...

vhdl intel fpga intel-fpga quartus

How to implement several independent devices on one FPGA?...

vhdl fpga intel-fpga

how to randomize the elements of a array in vhdl code?...

random vhdl intel-fpga

Can FPGA Stratix 3 memory handle large amount of data?...

memory size vhdl fpga intel-fpga

Why does printf with %lld return a different number than with %16x when using 64 bit (long long)?...

c intel-fpga

FPGA IO configuration: Effect of weak pull up/down on an output...

io fpga xilinx intel-fpga lattice-diamond

CMake add_custom_command fails with bin/sh:1 : ... not found...

cmake intel clion intel-fpga

Atlas-SoC board preloader troubleshooting...

preloader intel-fpga bare-metal

Can we include C source file in another way?...

c eclipse intel-fpga bare-metal

AHDL dff resets to it default value...

hdl intel-fpga

Can't build bootlader and kernel image for my DE0-Nano-SoC board...

yocto intel-fpga soc

Maximum clock frequency on DE1-SOC...

verilog fpga intel-fpga

Modelsim Warning: (vlog-2083) <protected>(<protected>): Carriage return (0x0D) is not fo...

intel fpga modelsim intel-fpga

Use dma transfert with Cyclone V Avalon-MM for PCIe...

dma intel-fpga pci-e quartus qsys

How to generate .rbf files in Altera Quartus?...

fpga intel-fpga quartus

Shifter output is always 0 when using concatenation and case...

verilog system-verilog modelsim intel-fpga