hdl Examples and Free Source Code

It would be nice to have Vec[Mem] in Chisel...

scala hardware hdl digital-logic chisel

Chisel: how to avoid errors NO DEFAULT SPECIFIED FOR WIRE...

scala hardware hdl digital-logic chisel

Assign vec to UInt ports...

scala hdl chisel

Enable On Function/Method Call...

verilog system-verilog hdl

Distinguish between simulation and HDL code generation in simulink...

matlab vhdl simulink hdl

using always@* | meaning and drawbacks...

verilog hdl system-verilog

what's the difference in position declaring variable in xilinx?...

verilog xilinx hdl

Fundamental Verilog Concepts...

verilog hdl

Shifting a Concatenate Register...

verilog hdl

Is it possible to avoid specifying a default in order to get an X in Chisel?...

hardware hdl synthesis digital-logic chisel

Override size of a parameter that is an array of a struct in systemverilog...

arrays verilog system-verilog hdl register-transfer-level

compiling Verilog code in Quartus...

verilog hdl intel-fpga

Bluespec $display within function...

hdl bluespec

writing a ripple carry adder in verilog...

verilog hdl

How do I express a boolean expression comprised of AND, OR and NOT using only AND and NOT?...

boolean-logic discrete-mathematics circuit hdl

Any benefits from implementing CSA versus just using multiplication symbol when synthesizing?...

verilog fpga hdl register-transfer-level asic

Are there any advantages to having fewer levels of wrappers in verilog?...

verilog hdl

SystemC how to get interactive user input...

c++verilog hdl systemc

Generate statement inside verilog task...

verilog hdl

Parameterized net width in Verilog...

verilog fpga hdl

How to write an array to text file ?VHDL code...

vhdl fpga hdl

How to display a 14 bit output onto a 2 digit display?...

hardware verilog fpga hdl

Is a <= a + 1 a good practice in VHDL?...

hardware vhdl xilinx hdl modelsim

Does "signal" imply δ delay in VHDL?...

signals vhdl hdl

VHDL: Properly clocking another component with respect to setup...

hardware vhdl fpga hdl

array and multiplexer in Verilog...

arrays verilog hdl

Simulator showing wrong input...

verilog xilinx hdl

If there exists two component of same name, one in package and other in architecture, which one is g...

vhdl hdl modelsim

Make HTTP Request from Verilog...

c++python verilog system-verilog hdl

Seven Segment Multiplexing on Basys2...

verilog fpga hdl synthesis multiplexing