How to convert Vec(n,Bool()) into UInt value...

How do you split modules into individual files using ChiselStage?...

Scala/Chisel Data to be connected must be hardware, not a bare Chisel type...

Scala Chisel Ripple Carry Adder Syntax...

Using existing Scala Class in new Class [Scala Chisel]...

option method of boolean Scala / Chisel...

generate register delay for simulation in chisel...

Differences between LazyModule and LazyModuleImp...

Why is ready signal always 0 in arbiter?...

Chisel: How to wait for signal assertion in ChiselScalatestTester?...

Scala Option Impact...

Creating string debug Vec for state machine...

Can I compute constants in software before Chisel begins designing hardware?...

Set-associative TLB on Rocket Chip...

Retrieve the reset value of RegInit...

Returning multiple elements for apply method...

Connecting Individual Modules - Chisel...

IP block generation/testing when using diplomacy. Possible to give dummy node?...

Rebased and now facing Scala dependency issues...

What do decoupled and irrevocable mean in Chisel?...

Demuxer : Unconnected Wires / firrtl error...

SyncReadMem generated verilog vs. Rocketchip emitted verilog...

What the difference between != and =/= in chisel?...

Chisel and Timing Constraints files...

Chisel Passing Enum type as IO...

Chisel: How to change module parameters from command line?...

How to Split a State Machine in multiple Classes or Traits in Chisel?...

How the mask can be used in aggregate memory in chisel?...

How to exchange certain bits of the register...

java.nio.file.NoSuchFileException: /home/jovyan/work/source/load-ivy.sc...