Is there an automated way to remove unnecessary targets from Makefile? I used ones generated by qmake, but I am to run them on machine doesn't have QT. Since the Makefile generated by qmake, it contains QT-related targets such as 1) "Makefile:" that call "$(QMAKE)" 2) "qmake:" ; as well as QT files in dependencies, such as "/usr/share/qt4/mkspecs/common/g++.conf" and so on.
Makefile: my_project.pro /usr/share/qt4/mkspecs/linux-g++/qmake.conf /usr/share/qt4/mkspecs/common/g++.conf \
/usr/share/qt4/mkspecs/common/unix.conf \
...
$(QMAKE) -spec /usr/share/qt4/mkspecs/linux-g++ -unix CONFIG+=debug -o Makefile my_project.pro
...
qmake: FORCE
@$(QMAKE) -spec /usr/share/qt4/mkspecs/linux-g++ -unix CONFIG+=debug -o Makefile my_project.pro
I have tried to remove those targets by hand and than could successfully compile project with them. The question is if there a simple automated way?
No there isn't. If you are using qmake, it means that you want to use it on computers with qt installed. As far as i know you shouldn't share your sources with Makefile's but with .pro files only. Anyone compiling it for himself should call qmake before make (or 'nmake' if you are using visual).
If you are not using qt at all, and use only qmake to generate Makefile, then there are alternatives (although not as simple as qmake, I admit) such as cmake or autoconf/automake.