Design and implement 16-bit carry-select adder with variable size (block sizes of 2-2-3-4-5)

Question

I have to design this in nand2tetris and I created a new folder on my desktop and did this

CHIP CarrySelectAdder16 {
    IN a[16], b[16], cin;  // 16-bit inputs and 1-bit initial carry-in
    OUT sum[16], cout;     // 16-bit sum and 1-bit carry-out

    PARTS:
    // Block 1: 2-bit addition
    CarrySelectBlock2(a=a[0..1], b=b[0..1], cin=cin, sum=sum[0..1], cout=carry1);

    // Block 2: 2-bit addition
    CarrySelectBlock2(a=a[2..3], b=b[2..3], cin=carry1, sum=sum[2..3], cout=carry2);

    // Block 3: 3-bit addition
    CarrySelectBlock3(a=a[4..6], b=b[4..6], cin=carry2, sum=sum[4..6], cout=carry3);

    // Block 4: 4-bit addition
    CarrySelectBlock4(a=a[7..10], b=b[7..10], cin=carry3, sum=sum[7..10], cout=carry4);

    // Block 5: 5-bit addition
    CarrySelectBlock5(a=a[11..15], b=b[11..15], cin=carry4, sum=sum[11..15], cout=cout);
}

This is the code i sued to calculate this I wrote Carryselectblock like this

CHIP CarrySelectBlock2 {
    IN a[2], b[2], cin;   // Two 2-bit input buses and carry-in
    OUT sum[2], carry;    // 2-bit sum output and carry-out

    PARTS:
    // First adder with cin = 0
    RippleCarryAdder2(a=a, b=b, cin=false, sum=sum0, carry=carry0);

    // Second adder with cin = 1
    RippleCarryAdder2(a=a, b=b, cin=true, sum=sum1, carry=carry1);

    // Muxes to select the correct sum bits based on cin
    Mux(a=sum0[0], b=sum1[0], sel=cin, out=sum[0]);
    Mux(a=sum0[1], b=sum1[1], sel=cin, out=sum[1]);

    // Mux to select the correct carry based on cin
    Mux(a=carry0, b=carry1, sel=cin, out=carry);
}

The error I'm getting is that I cannot use a sub bus of a internal node

Answer 1

In future, please specify what line in what file is generating the error.

However, the error message is explicitly telling you what the problem is -- you cannot use a subset of an internal bus as an input (ie: a=sum0[0] is not permitted).

You will have to redesign your chips to avoid this limitation.

Please refer to the book appendixes for more details on the format and limitations of NAND2Tetris HDL.