Question 1: Clarification on Connectivity and Memory Implementation in HART Core
In examining the HART core, I couldn't find any implementations beyond UART for IO and no presence of the AXI bus. How are components/objects connected in this scenario? Additionally, there's no sign of the mem_bus. Could someone elaborate on how memory is implemented in the HART core?
Question 2: Cache Implementation Possibility in HART Core
Given the absence of explicit mentions of certain components like mem_bus in the HART core, I'm curious about the feasibility of implementing cache within this architecture. Could someone provide insights into whether cache can be implemented in the HART core?
Question 3: Understanding HART Core Components: PS, Virtio_entropy, Clint, and Cell
While exploring the HART core, I encountered terms like PS, Virtio_entropy, Clint, and Cell. Could someone shed light on what these components represent within the HART architecture?
we are trying to create a diagram of the platform architecture of risc5 using simics
here is the tree of all the components:
https://drive.google.com/file/d/1XF10J5A-q-Nj6iq5QJSJLCATvO3Kvtfm/view?usp=sharing
General note on the RISC-V-simple design: the "hart" in the model is just hte processor core. The interrupt controllers and timers are considered separate memory-mapped devices.
In examining the HART core, I couldn't find any implementations beyond UART for IO and no presence of the AXI bus. How are components/objects connected in this scenario? Additionally, there's no sign of the mem_bus. Could someone elaborate on how memory is implemented in the HART core?
The memory bus is represented by the phys_mem object. To connect new things to the system, build a model of them and map their register banks into phys_mem. The RAM of the system is just an object mapped into that memory space. It all external to the core - all the core does is send memory operations to the phys_mem object.
Complete object map:
simics> list-objects -tree max-depth = 2 namespace = board
┐
├ boot ┐
│ └ image
├ cell ┐
│ └ ps
├ cell_context
├ cell_rec0
├ clint
├ console ┐
│ ├ con
│ └ serial
├ disk0 ┐
│ ├ disk_image
│ └ virtio_disk
├ disk1 ┐
│ ├ disk_image
│ └ virtio_disk
├ disk2 ┐
│ ├ disk_image
│ └ virtio_disk
├ eth
├ hart[0] ┐
│ └ extensions
├ hart[1] ┐
│ └ extensions
├ hart[2] ┐
│ └ extensions
├ hart[3] ┐
│ └ extensions
├ phys_mem
├ plic
├ ram ┐
│ └ image
├ serial0
├ uart0
├ virtio_entropy
└ virtio_net
And default memory map:
simics> board.phys_mem.map
┌───────────┬─────────────────────────────────┬──┬──────┬───────────┬──────┬────┬─────┬────┐
│ Base│Object │Fn│Offset│ Length│Target│Prio│Align│Swap│
├───────────┼─────────────────────────────────┼──┼──────┼───────────┼──────┼────┼─────┼────┤
│ 0x1000│board.boot │ │0x0000│0x0004_0000│ │ 0│ │ │
│0x0200_0000│board.clint.bank.regs │ │0x0000│ 0xc000│ │ 0│ │ │
│0x0c00_0000│board.plic.bank.regs │ │0x0000│0x0400_0000│ │ 0│ 8│ │
│0x1000_0000│board.uart0.bank.regs │ │0x0000│ 0x0011│ │ 0│ 8│ │
│0x1001_0000│board.virtio_net.bank.mmio │ │0x0000│0x0001_0000│ │ 0│ 8│ │
│0x1002_0000│board.disk0.virtio_disk.bank.mmio│ │0x0000│0x0001_0000│ │ 0│ 8│ │
│0x1003_0000│board.disk1.virtio_disk.bank.mmio│ │0x0000│0x0001_0000│ │ 0│ 8│ │
│0x1004_0000│board.disk2.virtio_disk.bank.mmio│ │0x0000│0x0001_0000│ │ 0│ 8│ │
│0x1008_0000│board.virtio_entropy.bank.mmio │ │0x0000│0x0001_0000│ │ 0│ 8│ │
│0x8000_0000│board.ram │ │0x0000│0x8000_0000│ │ 0│ │ │
└───────────┴─────────────────────────────────┴──┴──────┴───────────┴──────┴────┴─────┴────┘
Given the absence of explicit mentions of certain components like mem_bus in the HART core, I'm curious about the feasibility of implementing cache within this architecture. Could someone provide insights into whether cache can be implemented in the HART core?
To add a cache, you can use the simple-cache-tool. Search the documentation. Basically, the processor cores can send all accesses to a cache model. Chapter 5 in the Analyzer User Guide talks about this.
While exploring the HART core, I encountered terms like PS, Virtio_entropy, Clint, and Cell. Could someone shed light on what these components represent within the HART architecture?
Did you read https://community.intel.com/t5/Blogs/Products-and-Solutions/Software/Introducing-RISC-V-in-the-Simics-Simulator/post/1496444 ? The entropy device is explained there, it provides necessary randomness for SSH initialization.
The objects cell and cell.ps are used to manage Simics multithreaded simulations. See the Simics manuals, "API Reference Manual", Chapter 2, "Threading model" for more details. Searching the docs for "cell" would also have found this.
The object clint is the common RISC-V interrupt controller called CLINT.