VHDL set port range with a condition

Question

In VHDL, is it possible to set the range of a port using a condition which depends on a generic parameter? For example similar to this:

entity example is
    generic (
        IP_VERSION  : integer := 4
    );
    port (
        ip_address  : in std_logic_vector((127 when IP_VERSION = 6 else 31) downto 0)
    );
end example;

Answer 1

This is not currently possible as you have written, even with VHDL 2019 IIRC (when it sees some actual support).

The way to deal with this in all versions of VHDL is to write a function that is available in a package that returns the port size based on the input. for example:

package body example_pkg is
  function get_ip_addr_size (version : natural) return natural is
  begin
    case version is
      when 4 => return 32;
      when 6 => return 128;
      when others => report "Specified IP version (" & to_string(version) & ") is not valid" severity failure;  return 0;
    end case;
  end function;
end package body;


...

use work.example_pkg.all;


entity example is
    generic (
        IP_VERSION  : integer := 4
    );
    port (
        ip_address  : in std_logic_vector(get_ip_addr_size(IP_VERSION)-1 downto 0)
    );
end example;