I'm trying to write a 8 to 1 multiplexer code in Verilog, with the shortest possible delay.
Because I'm trying to decrease the "slack" in my project, and in this path the multiplexers takes around 3ns to perform.
Can you help me?
I tried these ways:
Implementation 1:
assign Y = (S == 3'b000) ? I1 :
(S == 3'b001) ? I2 :
(S == 3'b010) ? I3 :
(S == 3'b011) ? I4 :
(S == 3'b100) ? I5 :
(S == 3'b101) ? I6 :
(S == 3'b110) ? I7 :
(S == 3'b111) ? I8 :
32'hxxxx;
Implementation 2:
always @(*)
begin
case (S)
3'b000: Y = I1; //Choose First input if the selector equals "000"
3'b001: Y = I2; //Choose Second input if the selector equals "001"
3'b010: Y = I3; //Choose Third input if the selector equals "010"
3'b011: Y = I4; //Choose Forth input if the selector equals "011"
3'b100: Y = I5; //Choose Fifth input if the selector equals "100"
3'b101: Y = I6; //Choose sixth input if the selector equals "101"
3'b110: Y = I7; //Choose seventh input if the selector equals "110"
3'b111: Y = I8; //Choose eight input if the selector equals "111"
default: Y = 32'hxxxx; // Error state
endcase
end
Can I achieve better than that? And if I created 8to1 mux using two 4to1 muxes and one 2to1 mux, can I achieve better timing? If yes, what is the structure of the 4to1 and 2to1 code I need to write?
Your 2 Verilog code snippets are functionally equivalent. Verilog code is just the 1st step in creating hardware. In your case, the Verilog code has almost no affect on timing slack. It all depends on what the next steps in your design flow are: synthesis, place-and-route, etc.
You need to set the timing constraints in your synthesis tool appropriately to achieve your timing goals.
From a coding style perspective, I prefer the case statement since I think it better conveys the intent of the design.