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Operator & on VHDL

I'm not sure about how this operator works.

For example, if I had:

signal vector_a : std_logic_vector(4 downto 0) :=(others => '0');

vector_a <= vector_a(3 downto 0) & '1';

Would the result be "0 0 0 0 1" or "1 0 0 0 0" ?

In case of using 3 to 0 instead of 3 downto 0, would the result change?

Solution

  • "&" is the concatenate operator, and concatenates items from left to right.

    So in your example, the result in vector_a would be 0 0 0 0 1

    Using a different range would make no difference, the result would still be 0 0 0 0 1 when printed left to right. But it would affect the indexed values.