My folder structure is like below
/Myapp/main.c
/Myapp/f1.c
/Myapp/f1.h
/Myapp/Makefile
and my Makefile contest is
CC = gcc
main: main.o f1.o
$(CC) -o main main.o f1.o
main.o: main.c f1.h
f1.o: f1.c f1.h
I run the makefile at directory Myapp, and it works fine
BUT...when I move f1.h to a include folder like this:
/Myapp/main.c
/Myapp/f1.c
/Myapp/Makefile
/Myapp/include/f1.h
and Makefile add include path
CC = gcc
INCLUDE = ./include/
main: main.o f1.o
$(CC) -I$(INCLUDE) -o main main.o f1.o
main.o: main.c f1.h
f1.o: f1.c f1.h
it will show: make: *** No rule to make target `f1.h', needed by `main.o'. Stop.
This confuse me for a while.
After searching the relative question still can't resolve this simple problem
(I guess this is might be a relative dir problem, right?)
Thanks for help.
Change
main.o: main.c f1.h
f1.o: f1.c f1.h
to
main.o: main.c $(INCLUDE)f1.h
$(CC) -c -o main.o main.c -I$(INCLUDE)
f1.o: f1.c $(INCLUDE)f1.h
$(CC) -c -o f1.o f1.c -I$(INCLUDE)
you need to change path for f1.h related, add "include" for it