some errors of 'case <> is when......' in vhdl

Question

Error (10500): VHDL syntax error at decoder.vhd(22) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a sequential statement

This is the error:

Error (10500): VHDL syntax error at decoder.vhd(22) near text "when"; expecting ";"

It may be simple but I don't know what's the error.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
    A : in std_logic_vector(2 downto 0);
    G1 , G2A , G2B : in std_logic;
    Y : out std_logic_vector(7 downto 0)
);
end decoder;

architecture dec of decoder is
begin
process(A , G1 , G2A , G2B)
variable EN : std_logic;
begin
    EN := (G1 and (not(G2A)) and (not(G2B)));
    Y <="11111111";
    if(EN = '1') then
        csae (A) is
            when "000" => Y(0) <= '0';
            when "001" => Y(1) <= '0';
            when "010" => Y(2) <= '0';
            when "011" => Y(3) <= '0';
            when "100" => Y(4) <= '0';
            when "101" => Y(5) <= '0';
            when "110" => Y(6) <= '0';
            when others => Y(7) <= '0';
        end case;
    else Y <= "11111111";
    end if;
end process;
end dec;

Answer 1

You have a typo in your code, you wrote csae instead of case:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(
    A : in std_logic_vector(2 downto 0);
    G1 , G2A , G2B : in std_logic;
    Y : out std_logic_vector(7 downto 0)
);
end decoder;

architecture dec of decoder is
begin
process(A , G1 , G2A , G2B)
variable EN : std_logic;
begin
    EN := (G1 and (not(G2A)) and (not(G2B)));
    Y <="11111111";
    if(EN = '1') then
        csae (A) is /// <----- Should be case
            when "000" => Y(0) <= '0';
            when "001" => Y(1) <= '0';
            when "010" => Y(2) <= '0';
            when "011" => Y(3) <= '0';
            when "100" => Y(4) <= '0';
            when "101" => Y(5) <= '0';
            when "110" => Y(6) <= '0';
            when others => Y(7) <= '0';
        end case;
    else Y <= "11111111";
    end if;
end process;
end dec;