I have a Zynq7000 with softwares running on both cores. They interface with a FPGA which contains a lot of DMA. These DMA are used to perform data transfers that can go up to multiple MB.
My questions are:
Is it possible that, at some point, the combined access from the CPU and the AXI ports result in so much read and write requests that they stay pending an "unreasonably" period of time, or, even worse, that they are lost ?
Is there a method to estimate the worst case of DRAM accesses ?
Estimating by counting the cycles would be difficult. Better estimate can be had by a simple test - increase the throughput until it breaks. You could add some extra hardware which will stop the process when the "unreasonable" period of time stall happens and count it...
Estimating the worst case of DRAM access is adding together the CAS and RAS times (implies every access is to a different page)...