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makefilegnu-make

make: Command line variable propagation

If I have two Makefiles as below.

Makefile

all:
        make -f Makefile.app

Makefile.app

T=1

all:
        @echo $(T)

How does T get its value specified from command line, as shown below.

$ make T=10
# make[1]: Entering directory 'xxx'
10
# make[1]: Leaving directory 'xxx'

The make being used here is GNU Make 4.3.

Solution

  • A variable specified on the command line is considered an 'override' variable in that it will override any normal assignment in the makefile. More precisely, the when you assign a variable on the command line, that variable name gets marked with a property of override. Any normal attempts to assign a value to an override variable will not have any effect. The override variable will be inherited by a submake as if it were a command line assignment...

    You can use the override keyword in make to override an overridden variable. i.e. in your case, if you did

    override T=1

    in your makefile.app, then this would cause T to have a value of 1.

    See https://www.gnu.org/software/make/manual/html_node/Override-Directive.html for more information on this.