I am trying to implement a simple algorithm to add to floating point numbers using the IEEE.754 floating point notation. I have gotten quite far in the algorithm, but it does not give me the expected results
This is how the algorithm is looking so far. Only trying to add 1.0 + 1.0 at this point. The expected result is for the R0 register to be 0x40000000 at the point of hitting BX lr, which is the end of the program. The result I get now is a disappointing 0x40800000.
I compile with: arm-none-eabi-as -g -o float.o float.s arm-none-eabi-ld -0 float float.o
and then i run with Qemu qemu-arm -g 30005 ./part5
and step through with gdb gdb-multiarch file ./float target remote:30005
step through as normal with gdb
.section .data
@ Constants
exponent_mask: .word 0x7F800000
@ The two numbers we want to add
num1: .word 0x3f800000
num2: .word 0x3f800000
.section .text
.global main
main:
@ Load numbers directly
LDR r0, =num1
LDR r0, [r0]
LDR r1, =num2
LDR r1, [r1]
@ Load constant for exponent extraction just once
LDR r12, =exponent_mask
LDR r12, [r12]
@ Extract exponents
AND r2, r0, r12
AND r3, r1, r12
LSR r2, r2, #23
LSR r3, r3, #23
@ Clear the exponent parts
BIC r4, r0, r12
BIC r5, r1, r12
@ Add the implicit 1 to the fractions
ORR r4, r4, #0x00800000
ORR r5, r5, #0x00800000
@ Align exponents and adjust fractions
CMP r2, r3
BGT largerExponent
@ r3 has larger exponent
SUB r6, r3, r2
LSR r4, r4, r6
MOV r2, r3
B fractionsAligned
largerExponent:
SUB r6, r2, r3
LSR r5, r5, r6
fractionsAligned:
ADD r4, r4, r5 @ Add aligned fractions
@ Normalize if needed
TST r4, #0x01000000
BEQ doneNormalize
LSR r4, r4, #1
ADD r2, r2, #1
doneNormalize:
@ Construct the final number
LSL r2, r2, #23
ORR r0, r4, r2
BX lr
At the end of the program, the register values look like this: Reg values
After adding and normalizing, your code does not remove the leading 1 bit.
