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verilogsystem-veriloghardware

Confused about one Verilog command

Can anyone help me understand what the command below does?

reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;

I know reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}} means assign (ADDR_WIDTH+1) 0's to wr_ptr_reg, but what does the rest (the comma and wr_ptr_next) of the command do?

Solution

  • Verilog allows you to declare multiple signals in one statement, separated by commas.

    Your line of code declares 2 signals named:

    1. wr_ptr_reg
    2. wr_ptr_next

    Both signals are declared as the same type (reg) and have the same number of bits: ADDR_WIDTH + 1

    Verilog also allows for initializing a signal to a value on the same line as it is declared. All bits of the wr_ptr_reg signals are initialized to 0. Since there is no assignment to wr_ptr_next, all bits are initialized the unknown value (x), which is the default value for reg types.

    If you find the syntax confusing, you can always declare the signals with separate statements (which is a common practice):

    reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_next;