Search code examples
memorycpu-architectureram

Question on MRS Command and NOP Behavior in DDR3 Timing Diagram

I am currently studying DDR3 memory and am in the process of analyzing its timing diagrams.

DDR3 timing diagram with multiple signal lines

I am particularly intrigued by the section highlighted in red, which pertains to the MRS command. I have a couple of questions regarding this:

Does the MRS command stay active throughout the red-highlighted section, or does it transition into a NOP state for a specific duration?

For example:

Does the behavior align with what is shown in Diagram 1, where the MRS,ZQCL command remains active throughout? enter image description here Or does it align with Diagram 2, where it transitions into a NOP state for some time? enter image description here

Solution

  • Diagram 2 (padded with NOPs - or DES commands).

    The diagram seems to be taken from the next document, or similar (p. 8):

    https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/M15F2G16128A%20%282B%29_%20-40~95%E2%84%83.pdf

    Notice the marked comment in the diagram - i.e. it's filled with NOP or DES commands (Device Deselected).

    enter image description here

    In addition, the next diagram describes the tMRD (p. 10), which is the time between MRS to MRS. Notice tMRD is marked on your diagram as well.

    As you can see, they fill the time gap using NOPs.

    enter image description here

    You can find a similar diagram for tMOD, which is the time between MRS to non-MRS command, i.e., the time between the MRS to the ZQCL in your diagram.