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system-verilogassertionsystem-verilog-assertions

Signal Must Assert While Other Signal Is Asserted

I have a situation where a signal in a design must assert for at least one cycle while another signal is asserted for at least X cycles.

Desired Results:

Pass: pass example 1

Pass: pass example 2

Pass: pass example 3

Fail: fail example 1

I would like to write a property to check for this using SVA, essentially capturing that between the posedge and negedge of sig_1, sig_2 must have both $rose() and $fell().

I have tried something like...

property prop_sig_2_while_sig_1;
    @(posedge clk)
        $rose(sig_1) ##[0:$] $rose(sig_2) ##[0:$] $fell(sig_2) ##[0:$] $fell(sig_1);
endproperty : prop_sig_2_while_sig_1

but unfortunately, that did not work as desired.

Is there a simple and effective way to accomplish this?

Solution

  • What you probably want is

    property prop_sig_2_while_sig_1;
    @(posedge clk) $rose(sig_1) |-> sig_1 throughout sig_2[->1];
endproperty

    This gives you your desired results.