how to generate in vhdl in my testbench using a procedure two signals with different frequencies and delays

Question

I am currently trying to generate two signals in my testbench (VHDL) with a different delay, a different duty cycle and two different periods. The two signals must be carried out in parallel and not sequentially in a single main procedure containing the 6 parameters of the two signals (period1, delay1, duty cycle1, period2, delay2 and duty circle2). My problem is that the second signal is not activated at the desired moment but after the first signal has been exercised, which is logical since the execution is sequential. How can I get the second signal to activate at the desired Delay?

I've written two procedures for each signal and a main procedure for recalling them together. I hope to be able to have both signals activated at their respective delays independently of each other.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

library work;
use work.all;

entity paralell is
end paralell;

architecture paralell_arch of paralell is

constant c_CLOCK_PERIOD : time := 40 ns;
signal  L1   : std_logic := '0';
signal  L2  : std_logic := '0';  
    
begin
    UUT : entity work.paralel
     port map (
       clk => r_CLOCK,
        sig1 => L1,
       sig2 =>  L2,
       
       );   
  p_CLK_GEN : process is
  begin
    wait for c_CLOCK_PERIOD/2;
    r_CLOCK <= not r_CLOCK;
  end process p_CLK_GEN;

Simulation : process   -- main testing
procedure parametre_2(T6 : time; D6 : time; Delay6 : time) is
  begin
    L2 <= '0';
    if Delay6 >= 0 ns then
    wait for Delay6;
    end if;
    L2 <= '1';
    wait for D6;
    L2 <= '0';
    wait for (T6 - D6);
  end procedure parametre_2;
  
  procedure parametre_1(T5 : time; D5 : time; Delay5 : time) is
        begin
          L1 <= '0';
        if Delay5 >= 0 ns then
          wait for Delay5;
        end if;
          L1 <= '1';
        if D5 >= 0 ns then
          wait for D5;
        end if;
          L1 <= '0';
          wait for (T5 - D5);
        end procedure parametre_1;
      ``` 
      ``` 
 procedure parametre(T3 : time; D3 : time; Delay1 : time; T4 : time; D4 :time; Delay2 : time)is
  begin
   for i in 0 to 1 loop
     if i = 0 then 
         parametre_1(T3, D3, Delay1);
          elsif i= 1 then
         parametre_2(T4, D4, Delay2);
         end if;
         end loop;
         
end procedure parametre;
begin
parametre(400 us, 200 us, 10 ns , 100 us , 50 us,20 ns);
  report " Simulation finished successfully!" severity note;
  wait;
end process;
end paralell_arch;

Answer 1

I would agree with Jim on the simpler approach but here is an alternative for scheduling all events from one process that scales well if there are many clocks:

architecture test of two_clocks_in_one_process is
  signal clocks : std_logic_vector(1 to 2) := "00";
  constant delays : time_vector(clocks'range) := (10 ns, 20 ns);
  constant high_widths : time_vector(clocks'range) := (200 ns, 50 ns);
  constant periods : time_vector(clocks'range) := (400 ns, 100 ns);
begin
  clock_driver : process is
    variable next_event : time_vector(clocks'range) := delays;
  begin
    wait for minimum(next_event) - now;
    for idx in clocks'range loop
      if now = next_event(idx) then
        clocks(idx) <= '1', '0' after high_widths(idx);
        next_event(idx) := now + periods(idx);
      end if;
    end loop;
  end process;
end architecture;