Use PLL in Lattice Radiant

Question

Using Radiant to program Upduino v3.1 (ICE40UP5K) to implement a PLL created using the IP wizard. Once created, this is the .vhd code where initialized the PLL as well:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity blink is

    port (
        inclock : in std_logic;
        clockreset : in std_logic;
        outclock : out std_logic;
        led_r : out std_logic := '1'
    );

end blink;

architecture rtl of blink is
    signal count : integer := 0;
    signal led_state : std_logic := '1';    
begin

    mypll: entity GPLL port map(
    ref_clk_i => inclock,
    rst_n_i => clockreset,
    outcore_o => open,
    outglobal_o => outclock
    );
    
    BLINK_PROC : process(inclock)
    begin
        if rising_edge(inclock) then
            if count = 24e6 then
                count <= 0;
                led_state <= not led_state;
                led_r <= led_state;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
end architecture;

Then, assigned the variables to the following ports:
inclock -> 20, clockreset -> 6, led_r -> 41, outclock -> 10.

"Synthesize Design" and "Map Design" passed without any problem. During "Place & Route Design" I get the error:

ERROR <60001149> - All 1 iterations failed with design error(s). It is recommended to correct all design errors before running multiple iterations.
Please check the Place and Route reports (.par) for the individual iterations under the directory "C:\Users\212487877\my_designs\plltest1\impl_1\plltest1_impl_1_par.dir\5_1.par".
Done: error code 10

Checked the referred file, but couldn't find anything to solve the issue.

It is a code problem?
Am I assigning the pins incorrectly?

Answer 1

Simply switch outcore_o and outglobal_o. I only know verilog and there the following fails with a similiar error:

module main(    
    input   wire        clock_in,
    output  wire        clock_out
    );

testpll pll_inst(
    .ref_clk_i(clock_in), 
    .rst_n_i(1'b1), 
    .outcore_o(), 
    .outglobal_o(clock_out)) ;

endmodule

but this works:

module main(    
    input   wire        clock_in,
    output  wire        clock_out
    );

testpll pll_inst(
    .ref_clk_i(clock_in), 
    .rst_n_i(1'b1), 
    .outcore_o(clock_out), 
    .outglobal_o()) ;

endmodule

Additionally, it is recommended to use the GPLL_IN pin as PLL input, which would be pin 35 for iCE40UP5K-SG48I. However, I do not know what are the actual implication if a different input is used.