Basically I have two makefiles:
One at root which includes all the sub projects:
CXX="gcc"
CFLAGS="-I./include"
include subproject/make.mk
hello: hello.o subproject/test.o
$(CXX) -o hello hello.o subproject/test.o
hello.o: hello.c
$(CXX) $(CFLAGS) -o hello.o -c hello.c
I also have subproject/make.mk:
CFLAGS+="-Isubproject/include"
subproject/test.o: subproject/test.c
$(CXX) $(CFLAGS) -o subproject/hello.o -c subproject/test.c
As you can see the sub makefile adds to CFLAGS, however I want the modification to CFLAGS there to only appear in that sub makefile. Is there any way to separate the makefiles environments and only pass some variables? Or do I have to use separate variables?
I tried using recursive make however that is not expandable especially if one of my subprojects depend on another.
There is no way to modify a global variable so it only is in effect for some targets.
But, you can create a target-specific variable:
subproject/test.o: CFLAGS += -Isubproject/include
subproject/test.o: subproject/test.c
$(CXX) $(CFLAGS) -o subproject/hello.o -c subproject/test.c
However you have to do it for all the targets you want explicitly, there's no way to just automatically add it to all targets in an included file.
In make, inclusion happens at a very very low level. As far as the makefile parser is concerned it's essentially like you have combined all the makefiles into one big file (similar to how the C/C++ preprocessor works). The parser doesn't see where one file stops and another starts.