Search code examples
verilogsystem-veriloghdl

What is "first node name can be top of a hierarchy in Verilog" mean?

enter image description here

enter image description here

Is mod_2 and mod1 the top of the hierarchy?

module Middle;
initial
begin
  fork:mod_1
  #5 mod_2.mod_3.x=1;
  join
  fork:mod_2
    fork:mod_3
      reg x ;
    join
  join
end

endmodule

Above codes also works and I can even use module name at first node like codes below.

`timescale 1ns/1ns
module Middle;
initial
begin
  fork:mod_1
  #5 Middle.mod_2.mod_3.x=1;
  join
  fork:mod_2
    fork:mod_3
      reg x ;
    join
  join
end

endmodule

I think only the first node can be the top module name and others can be instance names or name block etc.

An upward name reference consist only of two parts separated by a period, so I think it is not upward name reference.

`timescale 1ns/1ns
module Top;
  Middle middle_0();
endmodule

module Middle;
  Below below_0();
  initial fork:a
    reg x;
  join
endmodule

module Below;
  initial #5 Middle.a.x=1;
endmodule

Is this upward reference? Standard Shows only two part consists of upward reference. syntax: module_identifier.item_name or scope_name.item_name

Solution

  • The first node name is simply the left most name in a pathname or dotted name as the LRM refers it by.

    name1 . name2 . name3 . ...

    There are specific rules for locating name1 when it appears as part of a dotted name that differ from when it appears as a simple identifier (See section 23.7 in the IEEE 1800-2017 SystemVerilog LRM).

    And there are different rules for module instance versus other block scopes. In this case, the top scope refers to the current module instance, but it can also refer to the top of any upward reference. Middle is both an upward reference and a top-level reference. If module middle were to get instantiated in a higher level module, the references to middle inside would still reference the same path.