VHDL what is wrong with simple rising_edge falling edge follower

Question

I have a very simple VHDL code, and I know it might not make much sense to use a code like this but yet I would not understand why, when I'm synthesizing, it is not allowed.

entity TopLevel is
    Port (
        Clk : in std_logic;
        GPIO_PIN : in std_logic;
        LED : out std_logic
    );
end TopLevel;

architecture Behavioral of TopLevel is
begin   
    process(GPIO_PIN) is
        begin
        if rising_edge(GPIO_PIN) then
            LED <= GPIO_PIN;
        elsif falling_edge(GPIO_PIN) then
            LED <= GPIO_PIN;
        end if;
    end process;
end Behavioral;

The error:

Signal LED cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

I could just use else instead of elsif, which is perfectly fine, heck it makes more sense. But I just don't understand why I cannot use this and why it raises this flag.

Answer 1

Synthesis tools are looking for some patterns to find HDL-processes which describe flipflops. These patterns only contain processes which are sensitive to a rising or a falling edge and never to both. The reason is that the synthesis libraries only contain flipflops, which are sensitive to a rising or to a falling edge, never to both.