I'm doing a Verilog project on quartus, and when I do the analysis and synthesis, quartus doesn't give me any errors.
When instead I try to compile the files on ModelSim, it gives me the following error:
** Error: C:/Users/deivi/OneDrive/Documents/ingegneria_progetti/EMBEDDED/prima_esercitazione/Gestione_sensori/conta_periodo.v(90): A begin/end block was found with an empty body. This is permitted in SystemVerilog, but not permitted in Verilog. Please look for any stray semicolons.
module conta_periodo (avvia, fatto, enable , start_count, ck, rst_l,rst_sync);
input avvia, rst_l, ck, enable;
output reg start_count, fatto, rst_sync;
reg [2:0] s_reg, s_next;
parameter [2:0] s_i = 3'b000, s_1 = 3'b001, s_2 = 3'b010, s_3 = 3'b011;
initial s_reg = 3'b000;
always @ (posedge ck) // memoria di stato
begin
if (rst_l) s_reg <= s_i;
else
begin
if (enable) s_reg <= s_next;
else s_reg <= s_reg;
end
end
always @ (*)
begin
s_next = s_reg;
case (s_reg)
s_i:
if (avvia) s_next = s_1;
else s_next = s_i;
s_1: s_next = s_2;
s_2: s_next = s_3;
s_3: s_next = s_i;
default: s_next = s_i;
endcase
end
always @ (s_reg)
begin
case (s_reg)
s_i: begin
start_count = 1'b0;
fatto =1'b0;
rst_sync=1'b1;
end
s_1: begin
start_count = 1'b1;
fatto =1'b0;
rst_sync=1'b1;
end
s_2: begin
start_count = 1'b1;
fatto =1'b0;
rst_sync=1'b1;
end
s_3: begin
start_count = 1'b0;
fatto =1'b1;
rst_sync=1'b0;
end
default: begin
start_count = 1'b0;
fatto =1'b0;
rst_sync=1'b0;
end
endcase;
end
endmodule
It's a state machine that works with another block.
Does anyone know why I get this error?
The error message says:
Please look for any stray semicolons.
There is a stray semicolon on line 90, as reported in the error message. Change:
endcase;
to:
endcase
You should not add semicolons after "end"-type keywords like end, endcase, endmodule, etc.