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assemblyriscv

Riscv: mhartid register

I had a quick question about the csr register mhartid in riscv. In the doc it is said that it correspond to the hardware thread id. But does a hardware thread correspond to a physical core or it is still an abstract notion? for exemple, can a core read different value in mhartid in the same execution sequence or a given core will always have a unique mhartid?

Solution

  • One core can have multiple threads (what Intel calls hyper-threading).

    See also: https://electronics.stackexchange.com/questions/580645/what-is-a-hardware-thread-in-risc-v

    The hardware thread ID will never spontaneously change during the execution of a sequence of instructions.