I'm using a makefile with two targets, both of which are variables. I can execute each target on the command line as follows:
make $(TARGET)
where TARGET is whatever file I'm outputting. However, before the target is made, zsh throws a "command not found" warning, which I assume means the shell is looking for a command called "TARGET" first. Is there a way to stop zsh from trying to find the command before make
gets to it? I have tried both make $(OUTPUT)
and make "$(OUTPUT)"
and both cause the "command not found" warning.
Output for reference:
> make "$(OUTPUT)"
zsh: command not found: OUTPUT
make: 'the-contest.odt' is up to date.
Makefile for reference:
OUTPUT=the-contest.odt
FINAL=the-contest.html
$(OUTPUT): the-contest.md
pandoc -o the-contest.odt the-contest.md
$(FINAL): the-contest.md
pandoc -o the-contest.html the-contest.md
The expression $(some command)
in most shells means "run some command
and substitute the output". So when you run make "$(OUTPUT)"
you are asking your shell to run a command named OUTPUT
, which is why you're getting a command not found error.
For what you're trying to do you probably want to restructure your Makefile, for example:
OUTPUT=the-contest.odt
FINAL=the-contest.html
.PHONY: output
output: $(OUTPUT)
$(OUTPUT): the-contest.md
pandoc -o the-contest.odt the-contest.md
$(FINAL): the-contest.md
pandoc -o the-contest.html the-contest.md
Now you can run:
make output