how to fix "found '0' definitions of operator + cannot determine exact overloaded matching definition for +"?

Question

Been trying to do my testbench in vhdl but the error "found '0' definitions of operator + cannot determine exact overloaded matching definition for +" keeps showing.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity system_tb is
end system_tb;

architecture Behavioral of system_tb is
    component system
        port (
                dataA : in STD_LOGIC_VECTOR(3 downto 0);
                dataB : in STD_LOGIC_VECTOR(3 downto 0);
                addA : in STD_LOGIC_VECTOR(2 downto 0);
                addB : in STD_LOGIC_VECTOR(1 downto 0);
                sel_ALU : in STD_LOGIC_VECTOR(2 downto 0);
                FA : in STD_LOGIC;
                FB : in STD_LOGIC;
                en0 : in STD_LOGIC;
                en1 : in STD_LOGIC;
                en2 : in STD_LOGIC;
                CLK:  in  STD_LOGIC;
                result : out STD_LOGIC_VECTOR(3 downto 0);
                carry: out STD_LOGIC;
                display : out STD_LOGIC_VECTOR(6 downto 0)
            );
     end component;
     
signal dataA : STD_LOGIC_VECTOR(3 downto 0);
signal dataB : STD_LOGIC_VECTOR(3 downto 0);
signal addA : STD_LOGIC_VECTOR(2 downto 0);
signal addB : STD_LOGIC_VECTOR(1 downto 0);
signal sel_ALU : STD_LOGIC_VECTOR(2 downto 0);
signal FA : STD_LOGIC:='0';
signal FB : STD_LOGIC;
signal en0 : STD_LOGIC;
signal en1 : STD_LOGIC;
signal en2 : STD_LOGIC;
signal CLK: STD_LOGIC :='0';
signal result : STD_LOGIC_VECTOR(3 downto 0):="0000";
signal carry: STD_LOGIC:='0';
signal display : STD_LOGIC_VECTOR(6 downto 0);

begin

uut:  system PORT MAP (
            dataA =>dataA,
            dataB =>dataB,
            addA =>addA,
            addB =>addB,
            sel_ALU =>sel_ALU,
            FA =>FA,
            FB =>FB,
            en0 =>en0,
            en1 =>en1,
            en2 =>en2,
            CLK=>CLK,
            result=>result,
            carry=>carry,
            display=>display
           );
process
    begin
        en0<='1';
        en1<='1';
        en2<='1';
        CLK<= not(CLK) after 15ms;
        sel_alu<="000";
        dataA<="0000";
        dataB<="0000";
        addA<="000";
        addB<="00";
        for k in 0 to 7 loop--recorre las operaciones de la ALU
            for j in 0 to 1 loop--recorremos los valores de FA
                FB <='0';
                for x in 0 to 1 loop--recorremos valores FB
                    if (FA='0') then
                        for i in 0 to 7 loop --recorre valores de AddA
                            wait for 20ns;
                            addA<=addA+1;
                        end loop;
                    else
                        for i in 0 to 15 loop --recorre DataA
                            wait for 20ns;
                            DataA<=DataA+1;
                        end loop;
                    end if;
                    if (FB='0') then
                        for l in 0 to 15 loop --recorre DataB
                            wait for 20ns;
                            dataB<=dataB+1;
                        end loop;
                    else
                        for l in 0 to 3 loop --recorre AddB
                            wait for 20ns;
                            AddB<=AddB+1;
                        end loop;
                    end if;
                    FB <= FB+1; --This is the line that shows the error
                end loop;
            end loop;
        end loop;
    end process;
end Behavioral;

std_logic_unsigned.all seems to work for other people but not for me. also tried with diferent libraries but does not work. Casting FB as unsigned did not work either.

Answer 1

This is because std_logic_unsigned (which is a non-standard VHDL package) only defines arithmetic operators for std_logic_vector type. Signal FB is type std_logic.

The easist solution is to simply negate FB.

FB <= not FB;