Writing a Makefile target for multiple libraries with different dependencies

Question

I have a makefile which builds multiple libraries named things like libx86.a and libvmx.a. The libraries have different inputs from variables named following a pattern like OBJ_libx86 and OBJ_libvmx. I have separate makefile targets for each of these libraries which run the same command with different inputs like so:

OBJ_libvmx = vmx.c.o vmx.S.o
OBJ_libx86 = mmu.c.o segments.S.o

libvmx.a: $(OBJ_libvmx)
    ar rcs $@ $^

libx86.a: $(OBJ_libx86)
    ar rcs $@ $^

Is there a way to do makefile expansion magic to have one rule which covers both of these cases?

I tried this, but I don't think $* expands correctly in that context:

%.a: $(OBJ_$*)
    echo dollar star is $*
    echo inputs are     $^
    ar rcs $@ $^

Answer 1

Well, the very simplest thing to do is just write it like this:

libvmx.a: vmx.c.o vmx.S.o
libx86.a: mmu.c.o segments.S.o

lib%.a:
        ar rcs $@ $^

There's no particular reason that you have to put the prerequisites on the same line as the target.