logic of shifting 0 4 times in efr32 cmuClock_GPIO setting

Question

in the variable bellow cmuClock of gpio is defined. i know what is << and bit wise or operations . but there are logical stuff like shifting 0 four times :-) shifting 0 4 times still will result in zero. What kind of registers are used in efr32 for this purpose? Thanks.

cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)//0<<4
                  | (CMU_NOSEL_REG << CMU_SEL_REG_POS)//0<<0
                  | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)//5<<8
                  | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)//2<<12
                  | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),//5<<17

Answer 1

Writing it this way makes the code maintainable.

If the value of CMU_NOPRESC_REG needs to change to something other than zero, you can just change one constant in one place, and the code still works.

If you take away the shift, then when you want to change the value of that bitfield then you can't just change one constant, you have to go through all the code and put the shifts back in.

(Note also that if you write (0 << N) then the compiler will never actually generate a shift instruction anyway, it will do the shift at compile time and insert the resulting value in the binary).