Upon a cache miss, the processor accesses RAM to read data and performs a prefetching operation, with data flowing from the RAM to the L3 cache, then the L2, and finally, L1.
Does the processor copy the same bloc in all cache levels during a prefetching?
Yes @erikeidt, and it also depends on the type of caches: inclusive or not. If it is inclusive, each lower cache level can hold the data from the higher levels. If not, the data can go directly from RAM to L1 cache.