VHDL Error "Expecting constant slice on LHS"

Question

I wrote a code. This should insert a "1" at a position, which is determined by the binary part of a signal E_reg_sig. The bits left to the "1" should be filled up by the fractional bits of a signal E_reg_sig.

There are some special cases:

1. The position is higher than the Output signals range: then all bits are set to high
2. There are more bits left right to the "1" than E_reg_sig has fractional bits: In this case the output should be filled up with the bits from E_reg_sig's fractional part, the rest should be "0"s
3. There is less space than E_reg_sig's bits widh: In this case the code should be filled up with the Bits from E_reg_sig from MSB to LSB till there are no bits from the output to fill up anymore

     library ieee;
     use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.fixed_pkg.all;
    use work.parameters.all;
    
    entity log_mvm is
      port (
    CLK:        IN  std_logic;
    E_reg: IN: ufixed(counter_log_mvm_WIDTH downto -(DATA_WIDTH_IN-2));
    F_reg: OUT: unsigned(DATA_WIDTH_IN-2 downto 0);
      );
    end log_mvm;
    architecture Behavioral of log_mvm is
    begin
    process(clk)
     variable insert_position : NATURAL;  
    if rising_edge(CLK) then
    
        insert_position:= to_integer(E_reg(E_reg'high downto 0));
    
        if insert_position > F_reg'high then
            F_reg<= (others=>'1');
        else 
            F_reg(insert_position)<='1';
         if insert_position>-1 then
            If insert_position>=(-E_reg'low) then
               F_reg(insert_position-1 downto insert_position+E_reg'low)<=unsigned(E_reg(-1 downto E_reg'low));
            else  
                F_reg(insert_position-1 downto 0)<=unsigned(E_reg(-1 downto -insert_position));
          END if;
          END IF;
        end if;
       
        END IF;
        END IF;
        end process;
    end Behavioral;

DATA_WIDTH_IN is defined as natural with the value 8

This codes works in simulation fine, but for synthezise, there is the error "[Synth 8-7138] Expecting constant slice on LHS" on part F_reg(insert_position-1 downto 0)<=unsigned(E_reg(-1 downto -insert_position));

How to avoid this

I am using VHDL 2008 with Vivad0 2021

Answer 1

You have to work with a loop:

for i in F_reg'range loop
    if i<=insert_position-1 then
        F_reg(i) <= E_reg(i-insert_position);
    end if;
end loop;