Bad operand types 'std_ulogic' and 'string(1 to 1)' from vhdl

Question

I've this error on my code at the line 13 and 27, on vhdl, do anyone know what's wrong?

LIBRARY IEEE;
USE ieee.std_logic_1164.all;

entity POLI is 
    port(A,B: in std_logic_vector(2 downto 0);
         x,y: in std_logic;
         S: out std_logic_vector(6 downto 0));
end POLI;

architecture codigo of POLI is
    begin
        process(x) begin
            if (x="1") then
                S(0)<=((A(0)and(not A(1))and A(2))or((not A(0))and A(1)and A(2)));
                S(1)<=((not A(0))and A(1)and (not A(2)));
                S(2)<=((not A(0))and (not A(2)));
                S(3)<=(((not A(0))and (not A(1))and (not A(2)))or ((not A(0))and A(1)and A(2)));
                S(4)<=(A(0)and (not A(1))and (not A(2)));
                S(5)<=(A(0)and (not A(1))and (not A(2)));
                S(6)<=(((not A(0))and A(1))or((not A(0))and A(2)));
            else
                S<="0000000";
            end if;
        end process;

        process(y) begin
            if (y="1") then
                S(1)<=(((not B(0))and (not B(2)))or((not b(0))and(not B(1))));
                S(2)<=((not B(0))and(not B(2)));
                S(4)<=(((not B(1))and B(0))or((not B(1))and B(2)));
                S(5)<=(B(0)and(not B(1)));
                S(6)<=(((not B(0))and B(1)));
             else
                S<="-------";
            end if;
        end process;
end codigo;

I tried on other computers and compilers, and all got the same problem

Answer 1

You have if x="1" then and if y = "1" then "" In VHDL represents a string (or a bitstring literal) both x and y are std_logic and hence not array types. In this instance, you should use ', as this is the character reference that std_logic uses for its values.

hence you should write.

if x = '1' then
....
if y = '1' then