How to separate digits from a two-digit number in VHDL

Question

I have my simple code in VDHL that seperates digit from 2-digit number, but when testing, my seperated digits remain unsigned (u). I have a hunch that the problem may be in the types of variables, when I use operations on them that they do not support. I use ghdl with gtkwave Variables in gtkwave

--FULL LOGIC--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity DigitSeparator is
    port(
        value: in unsigned(6 downto 0);
        leastSingnificantDigit: out unsigned(3 downto 0);
        mostSignificantDigit: out unsigned(3 downto 0)
    );
end entity DigitSeparator;

architecture DigitSeparator of DigitSeparator is
begin
    -- Set the outputs to 1111 1111 if the input is greater than 99
    process(value)
    begin
        if value > 99 then
            leastSingnificantDigit <= "1111";
            mostSignificantDigit <= "1111";
        else
            leastSingnificantDigit <= value mod 10;
            mostSignificantDigit <= value / 10;
        end if; 
    end process;
end architecture DigitSeparator;

--TEST BENCH--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity DigitSeparatorTB is
end entity DigitSeparatorTB;

architecture DigitSeparatorTB of DigitSeparatorTB is
    component DigitSeparator
        port(
            value: in unsigned(6 downto 0);
            leastSingnificantDigit: out unsigned(3 downto 0);
            mostSignificantDigit: out unsigned(3 downto 0)
        );
    end component DigitSeparator;


    signal value: unsigned(6 downto 0) := "0110000";
    signal leastSingnificantDigit: unsigned(3 downto 0);
    signal mostSignificantDigit: unsigned(3 downto 0);


begin
    kaka: DigitSeparator port map (value, leastSingnificantDigit, mostSignificantDigit);
    value <= "0110000", "1111111" after 100 ns, "1000010" after 200 ns;
end architecture DigitSeparatorTB;

Answer 1

The problem is when I try to assign a 4 bit variable (leastSingnificantDigit, mostSignificantDigit) a result that has 7 bits, so I have to guarantee that the result will only have 4 bits thanks to the parenthesis "3 downto 0"

This works:

leastSignificantDigit <= "mod" (value, 10)(3 downto 0);
mostSignificantDigit <= "/" (value, 10)(3 downto 0);