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FPGA Pin Polarity meaning

I have been assigning pins on a Lattice Seminconductor FPGA using Radiant Software. The FPGA is embedded on an evaluation board containing LEDs and buttons.

When opening the window to assign pins, every pin is desribed by a column named "polarity", as showed below.

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As it can be seen, pin H1 and J1 have opposite polarity. Within the avaluation board are connected to 2 different LEDs as showed below:

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So when H1 and J1 are connected to GND, the LED lights up. I therefore wrote an HDL that set the port to 0. In one test the port was assigned to pin H1, and in the second to the pin J1. Below the code:

use ieee.std_logic_1164.all;




entity LED is
port(
   LED_out     :   out std_logic);
end LED;

architecture Behavioral of LED is

constant LED_value: std_logic := '0';

begin

LED_out <= LED_value;

end Behavioral;

In both cases the LED0 and LED1 lighted up when the port was 0.

Before testing I assumed a negative polarity inverts whatever signal is going into/out the pin, but it doesn't seem to be the case.So what does "polarity" this refer to?

Solution

  • The pins of Lattice FPGAs can be used individually for single-end IO standards such as Low-Voltage-TTL (LVTTL). Some pins of these FPGAs can also be used in pairs for differential IO standards such as Low-Voltage-Differential-Signaling (LVDS).

    From what you have shown, the pins identified as PL24A and PL24B are a pin-pair that can be used for LVDS. The polarity for these pins refers to the standard “+” and “-" pins associated with LVDS. The polarity has no meaning when the pins are used individually for single-end IO standards.

    Lattice Diamond software has good built-in help ("Help > Lattice Diamond Help"). Try using this built-in help to search for information on “differential pins”.