library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity equation_tb is
end equation_tb;
architecture Behavioral of equation_tb is
signal x, y, z, t, w : std_logic;
signal F : std_logic;
begin
UUT : entity work.equation port map (x, y, z, t, w, F);
process
begin
x <= '0', '1' after 160 ns;
y <= '0', '1' after 80 ns, '0' after 160 ns, '1' after 240 ns;
z <= '0', '1' after 40 ns, '0' after 80 ns, '1' after 120 ns, '0' after 160 ns, '1' after 200 ns, '0' after 240 ns, '1' after 280 ns;
t <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns, '1' after 100 ns, '0' after 120 ns, '1' after 140 ns, '0' after 160 ns, '0' after 180 ns, '1' after 200 ns, '0' after 220 ns, '1' after 240 ns, '0' after 260 ns, '1' after 280 ns, '0' after 300 ns;
end process;
end Behavioral;
Hello, is there any way to write this in a simpler way. After "t" I have to write this for "w" and it will change in every 10ns, hence the line will be very long.
I tought about using for loop or if, but couldn't know what to do.
You can use separate processes for each signal. Since each process without a blocking wait will be repeated, this gives you cyclical signals as you want.
architecture Behavioral of equation_tb is
signal x : std_logic := '0';
signal y : std_logic := '0';
signal z : std_logic := '0';
signal t : std_logic := '0';
signal w : std_logic := '0';
signal F : std_logic;
begin
UUT : entity work.equation port map (x, y, z, t, w, F);
process
begin
wait for 160 ns;
x <= not x;
end process;
process
begin
wait for 80 ns;
y <= not y;
end process;
process
begin
wait for 40 ns;
z <= not z;
end process;
process
begin
wait for 20 ns;
t <= not t;
end process;
process
begin
wait for 10 ns;
w <= not w;
end process;
end Behavioral;
You probably had a typo in your sequence for t, as you wrote '0' after 160 ns, '0' after 180 ns. I ignored that.