Unknown syntax error near "wait for" statement VHDL

Question

My "wait for" statements in my test bench code are producing syntax errors, and I am unable to trace down the source of the error to fix it. The error that it is producing is:

Error: Syntax error near 'wait' Error: type error near ns ; current type time; expected type void Error: 'ns' is not a subprogram

Which I am not understanding since all examples including in a textbook for examples using the wait and wait for statements has been the exact same that I am using.

I've been looking at this testbench file for forever trying to figure out what this syntax error is. I can't determine if it is something earlier in my code with using an incorrect type, or missing a punctuation mark or what. This is supposed to just be a testbench for a state machine that will switch between add, subtract, multiply. A & B are 4 bit inputs, SEL is a button that when it is a 1 the state changes, and the CLK uses rising edge to pass any changes. Result is a 8 bit output.

I am even unable to run a simulation to test the entity and architecture as when I try to run the simulation on Vivado it won't because of the syntax near the wait statement. For context, in the code snippet below, the only underlined issue that Vivado has with it is by the wait for 10ns; line. If I format it as wait for 10 ns; it produces identical errors.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity HW9_TB is

end HW9_TB;

architecture Behavioral of HW9_TB is

    component HW9 is
    Port ( A : in signed (3 downto 0);
           B : in signed (3 downto 0);
           SEL : in STD_LOGIC;
           Q : out STD_LOGIC_VECTOR (1 downto 0);
           Result : out signed (7 downto 0);
           CLK : in STD_LOGIC);
    end component;

    signal A : signed (3 downto 0) := "0000";
    signal B : signed (3 downto 0) := "0000";
    signal SEL : std_logic := '0';
    signal CLK : std_logic := '0';

begin

    T1 : HW9 PORT MAP (
        A => A, B => B, SEL => SEL, CLK => CLK);
        
-- A=0, B=0, SEL=0, CLK=0
    A <=    "0000";     
    B <=    "0000"; 
    SEL <=  '0';    
    CLK <=  '0';    
    wait for 10ns;

Answer 1

You have two errors in your code:

1. wait is a sequential statement only allowed in a process, but you wrote it as a concurrent statement. Just think what it should mean outside of a process? All concurrent statements are executed in parallel.
2. The unit of the time needs to be separated from the value by white space.

A boiled-down and corrected version of your issue is:

entity TB is
end TB;

architecture Behavioral of TB is
begin
    --wait for 10 ns; -- Produces an error message, because not allowed here.

    process
    begin
        wait for 10 ns; -- Here it is allowed.
    end process;
end Behavioral;