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stm32f0

RM0091 interrupt priority > 4

in RM0091 I found Table36 which defines priorities > 4 (I believe that for CortexM0 maximum interrupt priority = 3). Does anyone know what these numbers are? enter image description here

Solution

  • You are correct that the priority of all interrupts on STM32F0xx is <= 3. (Note that this is for STM32F0xx, not all Cortex-M0).

    The numbers in the column marked "Priority" are interrupt numbers adjusted so that the first interrupt with settable priority is zero. It isn't really a useful column, you can safely ignore it.

    Note that ARM define a different interrupt numbering scheme, with zero set to the first interrupt which comes from a peripheral outside the processor core. This is used in all CMSIS headers (not just for STM32), for example "stm32f030x6.h":

    /******  Cortex-M0 Processor Exceptions Numbers */
  NonMaskableInt_IRQn         = -14,
  HardFault_IRQn              = -13,
  SVC_IRQn                    = -5,
  PendSV_IRQn                 = -2,
  SysTick_IRQn                = -1,

/******  STM32F0 specific Interrupt Numbers */
  WWDG_IRQn                   = 0,
  RTC_IRQn                    = 2,
  FLASH_IRQn                  = 3,
  RCC_IRQn                    = 4,
  EXTI0_1_IRQn                = 5,
  etc...

    This enum is used in the various functions for enabling and disabling interrupts etc.

    The only way that the interrupt numbers behave like a priority is if you set all the adjustable interrupt priorities to the same value. In that case only, the interrupts are handled in the order of their interrupt number, lowest first.