I am using an FPGA to generate a 32 bit value that is modified by counting a pulse train. The current implementation uses a 32 bit counter that counts up and down based on pulse and direction inputs. The output of the counter the value of interest.
I need to add another pulse train that I also want also modify the output value. Essentially I want to count both pulse trains and use the sum of the two as my value of interest.
This could be functionally achieved by independently counting the two pulse trains, and summing the output to a 32 bit register.
I am relatively new to FPGA's, and I'm wondering if there is any kind of dual input counter type of function block that would make this easier or more clear. If there was such a thing as a counter that will count two separate pulse trains it would simplify life.
Both pulse trains can be counting up or down, so the function block would have to allow for two pairs of step and direction signals, and the output would be the sum of the counts of the two up/down pulsetrains.
Is there any common function block to do such a thing, or is it necessary to use separate counters and sum them?
No, this cannot work, if both clocks are independent, and you use the clocks directly as clock signals for the counter.
In the first place this needs an edge-triggered flip-flop with two clock inputs. This does not exist, to my best knowledge.
The only serious solution is the one you describe: two separate counters, and an adder.
However, if you design your FPGA with a system clock high enough, you could develop a solution with just one counter. You can use a state machine to "mix" all input signals ( 2 clocks, 2 directions) into correct outputs to drive this counter. A clock high enough means that is has to be fast enough for the state machine to "catch" all possible situations.