I'm basing this off of Rocket-chip's implementation of CLINT. I don't believe this is in the RISC-V spec but the notion of CLINT shows up in a lot of RISC-V cores, so I've included the tag.
Currently, reset leaves timecmp untouched which can cause issues with some RTOS that rely on time comparison for OS ticks. https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/devices/tilelink/CLINT.scala#L96
Is the rationale behind not resetting timecmp that even though time resets, the device doesn't know what we want to reset timecmp to? Wouldn't it be a valid decision to reset it to 0 and allow the trap handler after the next interrupt to update it as opposed to requiring re-initialization in the firmware?
The reason to avoid adding a reset is related to wire fan-out. Having a register that takes in reset logic will increase the reset fan-out which increases routing resources and can potentially require dedicating a deeper pipeline for the system reset.