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vhdl

convert integer to std_logic

Suppose you have a loop

for i in 1 downto 0 loop
    for j in 1 downto 0 loop
        tS0 <= i;

But I need to convert the integer (which is natural) to std_logic. tS0 is declared as std_logic. I am only doing it one bit (0 or 1). That is, my i and j can only represent the value {0,1}.

I think I am heading to the wrong approach here. Can someone please tell me what should I do instead?

I don't think std_logic has to_unsigned method. i tried letting tS0 to be a vector (1 down to 0), and assigned like tS0(0) <= i, and etc. But it still didn't work out.

Thank you very much!

Solution

  • You will need to use a vector, either unsigned or std_logic, but it can be one bit long. ie:

    signal tS0 : unsigned (0 downto 0);
...
tS0 <= to_unsigned(i, tS0'length);

    ...or...

    signal tS0: std_logic_vector(0 downto 0);
...
tS0 <= std_logic_vector(to_unsigned(i,tS0'length);